
`include "defines.v"

module mux_offset (
    input  wire              rst,
    
    input  wire [`BUS_WIDTH] imm,
    input  wire [`BUS_WIDTH] r_data1,
    input  wire [`BUS_WIDTH] inst_addr,
    input  wire [1 :      0] pc_sel,

    output reg  [`BUS_WIDTH] offset
);


    always @(*) begin
        if (rst) begin
            offset = `ZERO_WORD;
        end
        else begin
            case (pc_sel)
                2'b00: begin
                    offset = 64'b100;
                end
                2'b01: begin
                    offset = imm;
                end
                2'b10: begin    // jalr
                    offset = (((r_data1 + imm) - inst_addr) & ~64'b1);
                end
                default: begin
                    offset = `ZERO_WORD;
                end
            endcase
        end
    end

    
endmodule
